1. Field of the Invention
The present invention relates to a multi-processor system provided with facility for allowing synchronous communications between processors arranged in a master and slave relationship.
2. Description of the Prior Art
For the purpose of accomplishing scientific computations or calculations at an increased speed, there has been developed a high-speed processor for executing at a high speed the arithmetic operations for those arrays which occur at a high frequency in the scientific calculation. The system or processing the arithmetic operations for the arrays at a high speed may be generally classified into two categories, i.e., a vector processor designed for processing one-dimensional vectors through pipeline at a high speed and a parallel processing system including a plurality of processors arranged in parallel with one another for executing processings in parallel. Although the application of the present invention is not restricted to the vector processor or the parallel processor, it seems convenient to elucidate the problems of the hitherto known systems in conjunction with the vector processor for facilitating the understanding of the underlying concept of the present invention.
The vector processor includes a vector processing mechanism for processing through pipeline at a high speed a series of array data (vector data) ordered in a sequence. However, it is not possible to process all the vector data with a single program. There exist those data which can only be processed through sequential processing (referred to as the scalar processing) as in the case of conventional general purpose computer. Under the circumstances, the vector processor includes in addition to the vector processing mechanism for pipeline-processing of the vector data at a high speed a scalar processing mechanism for realizing the function analogous to that of the hitherto known general purpose computer. Concerning the relationship to be established between the vector processing mechanism and the scalar processing mechanism incorporated in the vector processor, several approaches may be conceived. In many vector processors, however, the vector processing mechanism is physically separated from the scalar processing mechanism.
As an example of the processor incorporating the Vector processing mechanism and the scalar processing mechanism described above, there can be mentioned a processor disclosed in Japanese Patent Unexamined Publication No. 58-114274. The vector processor disclosed in this publication is composed of a scalar processing unit corresponding to the aforementioned scalar processing mechanism and a vector processing unit corresponding to the vector processing mechanism mentioned above.
More specifically, in the case of the processor system disclosed in Japanese Patent Unexamined Publication 58-114274, the vector processor is activated only after a previous or preparatory setting procedure such as loading of address data required for the vector processing in registers incorporated in the vector processor which has been executed by the scalar processor. Upon completion of the vector processing, the vector processor informs the scalar processor of the completion of vector processing by issuing an interrupt to the scalar processor or by taking advantage of the test performed by the scalar processor. On the other hand, the scalar processor executes predetermined scalar processing by utilizing the results of the vector processing. In this manner, in the case of this known system, all the data required for the vector processing are placed in the vector processor before activation of the latter. It is however noted that each of the vector instructions commanding the vector processing does not require all the data to be supplied from the scalar processor. Thus, execution of a vector instruction which requires only a part of the data supplied from the scalar processor involves a problem of wasteful loss of time (dead time), because the execution of such a vector instruction is allowed only after all the data have been set.
As described above, the scalar processor can perform the scalar processing after completion of the vector processing in the vector processor by utilizing the results of the vector processing. In this connection, it is also noted that each of the scalar instructions commanding the scalar processing does not require all the results of the vector processing. In other words, execution of a scalar instruction which requires only a part of the results of the vector processing has to wait for the completed execution of all the vector processings, which in turn means that wasteful loss of time is involved, giving rise to an additional problem.